Authors: Ni, WJ; Wang, XL; Xu, ML; Wang, Q; Feng, C; Xiao, HL; Jiang, LJ; Li, W
IEEE ELECTRON DEVICE LETTERS
Volume: 40 Issue: 5 Pages: 698-701 Published: MAY 2019 Language: English Document type: Article
DOI: 10.1109/LED.2019.2908253
Abstract:
The reliability of gate dielectrics is one of the key issues in SiC Trench MOSFET. While reducing the gate oxide electric field in OFF state through dedicated shielding structures by various designs, JFET resistances are often introduced. In this letter, a new asymmetric cell structure, tilt implanted 4H-SiC trench MOSFET (ACTI-TMOS) is proposed. This approach achieves a better trade-off between gate oxide electric field and specific ON-resistance (R-ON). The 2D numerical simulation was used to compare ACTI-TMOS with double trench MOSFET and gate bottom p-well trench MOSFET. The maximumgate oxide electric field of the ACTI-TMOS is 42.1% and 6.5% lower in OFF state compared to the other two designs. Both gate charge (Q(G)) and gate drain charge (Q(GD)) are significantly improved. The results show that ACTI-TMOS is a more attractive device structure.
全文链接：https://ieeexplore.ieee.org/document/8676293